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6 Command Interface
There are two types of bus cycles and timing sequences that occur in the IDE interface, PIO and Multi-Word
DMA (MDMA) as well as Ultra DMA (UDMA).
Figure 1 and Figure 2 show the read and write timing diagrams. Table 19, and Table 20 specify the read and
write timing parameters for PIO and MDMA mode, respectively.
6.1 PIO Mode
The timing waveforms for True IDE mode and True IDE DMA mode of operation in this section are drawn
using the conventions in the ATA-7 specification. Signals are shown with their asserted state as High
regardless of whether the signal is actually negative or positive true. Consequently, the – IORD, the
-IOWR and the – IOCS16 signals are shown in the waveforms inverted from their electrical states on the bus.
Figure 1: True IDE PIO mode Read/Write waveforms
1.
2.
3.
The device addresses consists of ?CS0, ?CS1, and A2 -A0.
The Data I/O consist of D15-D0 (16-bit) or D7-D0 (8 bit).
?IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.
Table 19: True IDE PIO mode Read/Write timing (1)
Parameter
Symbol
Mode 0
(ns)
1
(ns)
2
(ns)
3
(ns)
4
(ns)
Cycle time (min)
t 0
(2)
600
383
240
180
120
Address Valid to – IORD/-IOWR setup (min)
t 1
70
50
30
30
25
-IORD/-IOWR (min)
-IORD/-IOWR (min) Register (8 bit)
t 2
t 2
(2)
(2)
165
290
125
290
100
290
80
80
70
70
t 2i
-IORD/-IOWR recovery time (min)
-IOWR data setup (min)
-IOWR data hold (min)
-IORD data setup (min)
(2)
t 3
t 4
t 5
-
60
30
50
-
45
20
35
-
30
15
20
70
30
10
20
25
20
10
20
-IORD data hold (min)
t 6z
(3)
5
5
5
5
5
-IORD data tri-state (max)
Address valid to – IOCS16 assertion (max)
t 7
t 8
(4)
(4)
30
90
30
50
30
40
30
NA
30
NA
Address valid to – IOCS16 released (max)
-IORD/-IOWR to address valid hold
t 7
t 9
60
20
45
15
30
10
NA
10
NA
10
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
P-120_data_sheet_PA-QxBO_Rev100.doc
Page 12 of 76
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